KOD

–* Filname: mux_comp.vhd

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;

Entity Muxar is
port ( REX,RAC,RRG : in std_logic;
ACC,Dout,Data_in : in std_logic_vector(7 downto 0);
Data_buss : out std_logic_vector(7 downto 0));
end;
Architecture Muxar_Block of Muxar is
begin
process(REX, RRG, Data_in, Dout, ACC)
begin
if REX = ‘1’ then
Data_buss <= Data_in;
elsif RRG = ‘1’ then
Data_buss <= Dout;
else
Data_buss <= ACC;
end if;
end process;
end;

–************************* Description : ALU *******************************
Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_signed.ALL;

Entity ALU is
port( databuss: in std_logic_vector (7 downto 0);
AOP: in std_logic_vector (4 downto 0);
WFL: in std_logic;
WAC: in std_logic;
clk: in std_logic;
reset: in std_logic;
opy_flag: in std_logic;
re_flag: in std_logic;
ack: out std_logic_vector (7 downto 0);
Y: out std_logic_vector (7 downto 0);
Flag: inout std_logic_vector (2 downto 0));
end;
Architecture RTL of ALU is
signal Y_dummy: std_logic_vector (7 downto 0);
signal Flag_sig: std_logic_vector (2 downto 0);
signal overflow: std_logic;
signal zero: std_logic;
signal neg: std_logic;
signal ack_b: std_logic_vector(7 downto 0);
signal AOP_b: std_logic_vector (2 downto 0);
begin
ack<=ack_b;
AOP_b <= AOP (2 downto 0); process (AOP, databuss, ack_b) begin case AOP is when “01000” => Y_dummy <= not databuss; when “10000” => Y_dummy <= databuss and ack_b ; when “11000” => Y_dummy <= databuss or ack_b; when “00010” => Y_dummy <= databuss+1; when “00011” => Y_dummy <= databuss-1; when “00110” => Y_dummy <= databuss+ack_b; when “00111” => Y_dummy <= databuss-ack_b; when others => Y_dummy <= databuss;
end case;
end process;
Y <= Y_dummy;
process (Y_dummy, AOP_b, databuss(7), ack_b(7))
begin
if Y_dummy = “00000000” then
zero<= ‘1’;
else
zero<= ‘0’;
end if;
if Y_dummy(7) = ‘1’ then
neg <=’1′;
else
neg <=’0′;
end if;

if AOP_b = “110” then
if databuss(7) =’0′ and ACK_B(7) =’0′ and Y_dummy(7) = ‘1’ then
overflow <= ‘1’;
elsif databuss(7) =’1′ and ACK_b(7) =’1′ and Y_dummy(7) = ‘0’ then
overflow <= ‘1’;
else
overflow <= ‘0’;
end if;
elsif AOP_b = “111” then
if databuss(7) = ‘1’ and ack_b(7) = ‘0’ and Y_dummy(7) = ‘0’ then
overflow <= ‘1’;
elsif databuss(7) = ‘0’ and ack_b(7) = ‘1’ and Y_dummy(7) =’1′ then
overflow <= ‘1’;
else
overflow <= ‘0’;
end if;
elsif AOP_b = “010” then
if ack_b(7) =’0′ and Y_dummy(7) = ‘1’ then
overflow <=’1′;
else
overflow <=’0′;
end if;
elsif AOP_b = “011” then
if ack_b(7) = ‘1’ and Y_dummy(7)=’0′ then
overflow <= ‘1’;
else
overflow <=’0′;
end if;
else
overflow <= ‘0’;
end if;
end process;

process (clk, reset)
begin
if reset =’1′ then
Flag <= “000”;
Flag_sig <= “000”;
elsif clk’event and clk=’1′ then
if WFL = ‘1’ then
Flag(0) <= neg;
Flag(1) <= zero;
Flag(2) <= overflow;
end if;
if copy_Flag =’1′ then
Flag_sig <= Flag;
end if;
if re_Flag = ‘1’ then
Flag <= Flag_sig;
end if;
end if;
end process;

process (clk, reset)
begin
if reset=’1′ then
ack_b <= (others =>’0′);
elsif clk’event and clk=’1′ then
if WAC = ‘1’ then
ack_b <= Y_dummy;
end if;
end if;
end process;
end;

–* DESCRIPTION : Register Bank ***********************************************

Library ieee;
Use ieee.std_logic_1164.all;

entity REG is
port ( clk, reset, selekt : in std_logic;
WRG : in std_logic;
WBR : in std_logic;
addr : in std_logic_vector (2 downto 0);
D_IN : in std_logic_vector (7 downto 0);
D_OUT: out std_logic_vector (7 downto 0));
end;
architecture REGBANK of REG is
signal R0_0 :std_logic_vector(7 downto 0);
signal R0_1 :std_logic_vector(7 downto 0);
signal R0_2 :std_logic_vector(7 downto 0);
signal R0_3 :std_logic_vector(7 downto 0);
signal R0_4 :std_logic_vector(7 downto 0);
signal R0_5 :std_logic_vector(7 downto 0);
signal R0_6 :std_logic_vector(7 downto 0);
signal R0_7 :std_logic_vector(7 downto 0);
signal R1_0 :std_logic_vector(7 downto 0);
signal R1_1 :std_logic_vector(7 downto 0);
signal R1_2 :std_logic_vector(7 downto 0);
signal R1_3 :std_logic_vector(7 downto 0);
signal R1_4 :std_logic_vector(7 downto 0);
signal R1_5 :std_logic_vector(7 downto 0);
signal R1_6 :std_logic_vector(7 downto 0);
signal R1_7 :std_logic_vector(7 downto 0);
signal adr :std_logic_vector(2 downto 0);
signal RB :std_logic;
signal sel0 :std_logic;
signal sel1 :std_logic;
signal sel2 :std_logic;
signal sel3 :std_logic;
signal sel4 :std_logic;
signal sel5 :std_logic;
signal sel6 :std_logic;
signal sel7 :std_logic;
signal sel8 :std_logic;
signal sel9 :std_logic;
signal sel10 :std_logic;
signal sel11 :std_logic;
signal sel12 :std_logic;
signal sel13 :std_logic;
signal sel14 :std_logic;
signal sel15 :std_logic;
begin
adr <= addr(2 downto 1) & (addr(0) or selekt);
process(clk,reset)
begin
if reset =’1′ then
rb<=’0′;
elsif clk’event and clk=’1′ then
if wbr =’1′ then
rb<=addr(0);
end if;
end if;
end process;
process (rb, adr)
begin
sel0 <= ‘0’;
sel1 <= ‘0’;
sel2 <= ‘0’;
sel3 <= ‘0’;
sel4 <= ‘0’;
sel5 <= ‘0’;
sel6 <= ‘0’;
sel7 <= ‘0’;
sel8 <= ‘0’;
sel9 <= ‘0’;
sel10 <= ‘0’;
sel11 <= ‘0’;
sel12 <= ‘0’;
sel13 <= ‘0’;
sel14 <= ‘0’;
sel15 <= ‘0’;

if rb =’0′ and adr=”000″ then
sel0 <=’1′;
elsif rb =’0′ and adr=”001″ then
sel1 <=’1′;
elsif rb =’0′ and adr=”010″ then
sel2 <=’1′;
elsif rb =’0′ and adr=”011″ then
sel3 <=’1′;
elsif rb =’0′ and adr=”100″ then
sel4 <=’1′;
elsif rb =’0′ and adr=”101″ then
sel5 <=’1′;
elsif rb =’0′ and adr=”110″ then
sel6 <=’1′;
elsif rb =’0′ and adr=”111″ then
sel7 <=’1′;
elsif rb =’1′ and adr=”000″ then
sel8 <=’1′;
elsif rb =’1′ and adr=”001″ then
sel9 <=’1′;
elsif rb =’1′ and adr=”010″ then
sel10 <=’1′;
elsif rb =’1′ and adr=”011″ then
sel11 <=’1′;
elsif rb =’1′ and adr=”100″ then
sel12 <=’1′;
elsif rb =’1′ and adr=”101″ then
sel13 <=’1′;
elsif rb =’1′ and adr=”110″ then
sel14 <=’1′;
else
sel15 <=’1′;
end if;
end process;

REGISTERBANK:process(clk,reset)
begin
if reset = ‘1’ then
R0_0 <= (others => ‘0’);
R0_1 <= (others => ‘0’);
R0_2 <= (others => ‘0’);
R0_3 <= (others => ‘0’);
R0_4 <= (others => ‘0’);
R0_5 <= (others => ‘0’);
R0_6 <= (others => ‘0’);
R0_7 <= (others => ‘0’);
R1_0 <= (others => ‘0’);
R1_1 <= (others => ‘0’);
R1_2 <= (others => ‘0’);
R1_3 <= (others => ‘0’);
R1_4 <= (others => ‘0’);
R1_5 <= (others => ‘0’);
R1_6 <= (others => ‘0’);
R1_7 <= (others => ‘0’);
elsif clk’event and clk =’1′ then
if WRG = ‘1’ then
if sel0 =’1′ then
R0_0 <= D_IN;
elsif sel1 =’1′ then
R0_1 <= D_IN ;
elsif sel2 =’1′ then
R0_2 <= D_IN ;
elsif sel3 =’1′ then
R0_3 <= D_IN ;
elsif sel4 =’1′ then
R0_4 <= D_IN ;
elsif sel5 =’1′ then
R0_5 <= D_IN ;
elsif sel6 =’1′ then
R0_6 <= D_IN ;
elsif sel7 =’1′ then
R0_7 <= D_IN ;
elsif sel8=’1′ then
R1_0 <= D_IN ;
elsif sel9 =’1′ then
R1_1 <= D_IN ;
elsif sel10 =’1′ then
R1_2 <= D_IN ;
elsif sel11 =’1′ then
R1_3 <= D_IN ;
elsif sel12=’1′ then
R1_4 <= D_IN ;
elsif sel13=’1′ then
R1_5 <= D_IN ;
elsif sel14=’1′ then
R1_6 <= D_IN ;
else
R1_7 <= D_IN ;
end if;
end if;
end if;
end process;

Data_out:process ( sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, sel8, sel9, sel10,
sel11, sel12, sel13, sel14, sel15, R0_0, R0_1, R0_2, R0_3, R0_4, R0_5,
R0_6, R0_7, R1_0, R1_1, R1_2, R1_3, R1_4, R1_5, R1_6, R1_7)
begin
if sel0 =’1′ then
D_OUT <= R0_0;
elsif sel1 =’1′ then
D_OUT <= R0_1;
elsif sel2 =’1′ then
D_OUT <= R0_2;
elsif sel3 =’1′ then
D_OUT <= R0_3;
elsif sel4 =’1′ then
D_OUT <= R0_4;
elsif sel5 =’1′ then
D_OUT <= R0_5;
elsif sel6 =’1′ then
D_OUT <= R0_6;
elsif sel7 =’1′ then
D_OUT <= R0_7;
elsif sel8 =’1′ then
D_OUT <= R1_0;
elsif sel9 =’1′ then
D_OUT <= R1_1;
elsif sel10 =’1′ then
D_OUT <= R1_2;
elsif sel11 =’1′ then
D_OUT <= R1_3;
elsif sel12 =’1′ then
D_OUT <= R1_4;
elsif sel13 =’1′ then
D_OUT <= R1_5;
elsif sel14 =’1′ then
D_OUT <= R1_6;
else
D_OUT <= R1_7;
end if;
end process;
end;

–* DESCRIPTION : Instruction Register ***************************************
Library ieee;
Use ieee.std_logic_1164.ALL;
Entity IR is
port(clk, reset, WIR : in std_logic;
Data : in std_logic_vector (7 downto 0);
IR5 : out std_logic_vector (4 downto 0);
IR3 : out std_logic_vector (2 downto 0));
End;
Architecture Instruction of IR is
begin
process (clk, reset)
begin
if reset = ‘1’ then
IR5 <= (others =>’0′);
IR3 <= (others =>’0′);
elsif clk’event and clk = ‘1’ then
if WIR = ‘1’ then
IR5 <= Data (7 downto 3);
IR3 <= Data (2 downto 0);
end if;
end if;
end process;
end;

— Description : Interrupt input **********************************

Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;

Entity iq is
port (clk, reset, IRQ : in std_logic;
X_in : in std_logic_vector (4 downto 0);
IRQ_till_IMASK : out std_logic;
X_till_FSEL : out std_logic_vector (4 downto 0));
end;
Architecture rtl of iq is
begin
process (clk, reset)
begin
if reset=’1′ then
X_till_FSEL <= (others => ‘0’);
IRQ_till_IMASK <= ‘0’;
elsif clk’event and clk=’1′ then
X_till_FSEL <= X_in;
IRQ_till_IMASK <= IRQ;
end if;
end process;
end;

— Description : RAM16X1s *****************************************
Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;

Entity RAM16X1s is
port(we,d,wclk,a0,a1,a2,a3 : in std_logic;
O : out std_logic);
end;
Architecture behv of RAM16X1s is
signal adr : std_logic_vector(3 downto 0);
signal q : std_logic_vector(15 downto 0);
begin
adr<=a3 & a2 & a1 & a0;
process(wclk)
begin
if wclk’event and wclk=’1′ then
if we=’1′ then
q(conv_integer(adr))<=d;
end if;
end if;
end process;
O<=q(conv_integer(adr));
end;

— Description : STACK ******************************************

Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;

Entity stack is
port(clk, wst : in std_logic;
sp : in std_logic_vector(3 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0));
end;
Architecture rtl of stack is
COMPONENT RAM16X1s
port(we,d,wclk,a0,a1,a2,a3 : in std_logic;
O : out std_logic);
end COMPONENT;

— komenteras bort vid syntes:
For all : RAM16X1s use entity work.RAM16X1s(behv);
begin
RAM : for i in 0 to 15 generate
L : RAM16X1s port map(wst,din(i),clk,sp(0),
sp(1),sp(2),sp(3),dout(i));
end generate;
end;

— Description : STACK PEKARE *************************************************

Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;

Entity SP is
port(clk,reset,isp,dsp : in std_logic;
sp : out std_logic_vector(3 downto 0));
end;

Architecture rtl of SP is
signal count : std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset=’1′ then
count<=”0000″;
elsif clk’event and clk=’1′ then
if isp=’1′ then
count<=count+1;
elsif dsp=’1′ then
count<=count-1;
end if;
end if;
end process;
sp<=count;
end;

— ****************************************
— Description : Address_controller

Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;

Entity Addr is
port (databus : in std_logic_vector (7 downto 0);
stack_in : in std_logic_vector (15 downto 0);
SPA : in std_logic_vector (1 downto 0);
WHA : in std_logic;
WLA : in std_logic;
WPC : in std_logic;
IPC : in std_logic;
SAR : in std_logic;
reset : in std_logic;
clk : in std_logic;
stack_out : out std_logic_vector (15 downto 0);
address_out : out std_logic_vector (15 downto 0));
end;
Architecture block_7 of Addr is
signal H_int: std_logic_vector(7 downto 0);
signal L_int: std_logic_vector(7 downto 0);
signal address_int: std_logic_vector(15 downto 0);
signal H_L_int: std_logic_vector(15 downto 0);
signal PC_sel_int: std_logic_vector(15 downto 0);
signal stack_out_b: std_logic_vector(15 downto 0);
begin
address_int<=H_int & L_int;
H_L_int<=H_int & databus;
stack_out<=stack_out_b;
process (clk, reset)
begin
if reset = ‘1’ then
H_int <= (others => ‘0’);
L_int <= (others => ‘0’);
stack_out_b <= (others =>’0′);
elsif clk’event and clk = ‘1’ then
if WHA = ‘1’ then
H_int<=databus;
elsif WLA=’1′ then
L_int<= databus;
end if;
if WPC=’1′ then
stack_out_b<=pc_sel_int;
end if;
if IPC=’1′ then
stack_out_b<=stack_out_b + 1; end if; end if; end process; PCSEL:BLOCK begin process (SPA, H_L_int, stack_in) begin case SPA is when “00” =>pc_sel_int<=H_L_int; when “01” =>pc_sel_int<=stack_in; when others =>pc_sel_int<=(3=>’1′, others=>’0′);
end case;
end process;
end BLOCK;
ASEL:BLOCK
begin
process (SAR, address_int,stack_out_b)
begin
if SAR=’1′ then
address_out<=address_int;
else
address_out<= stack_out_b;
end if;
end process;
end BLOCK;
end;

— *******************************************************************
— Description : Display Controller

Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;
Entity DISPLAY is
port(clk, reset, WDP : in std_logic;
ACC : in std_logic_vector(7 downto 0);
DPY1,DPY2 : out std_logic_vector(6 downto 0));
end;
Architecture rtl of DISPLAY is
signal D1 : std_logic_vector(6 downto 0);
signal D2 : std_logic_vector(6 downto 0);
signal A1,A2 : std_logic_vector(3 downto 0);
begin
A1<=ACC(7 downto 4);
A2<=ACC(3 downto 0);
process(A1,A2)
begin
if A1=”0000″ then
D1<=”1000000″;
elsif A1=”0001″ then
D1<=”1111001″;
elsif A1=”0010″ then
D1<=”0100100″;
elsif A1=”0011″ then
D1<=”0110000″;
elsif A1=”0100″ then
D1<=”0011001″;
elsif A1=”0101″ then
D1<=”0010010″;
elsif A1=”0110″ then
D1<=”0000010″;
elsif A1=”0111″ then
D1<=”1111000″;
elsif A1=”1000″ then
D1<=”0000000″;
elsif A1=”1001″ then
D1<=”0011000″;
elsif A1=”1010″ then
D1<=”0001000″;
elsif A1=”1011″ then
D1<=”0000011″;
elsif A1=”1100″ then
D1<=”1000110″;
elsif A1=”1101″ then
D1<=”0100001″;
elsif A1=”1110″ then
D1<=”0000110″;
else
D1<=”0001110″;
end if;
if A2=”0000″ then
D2<=”1000000″;
elsif A2=”0001″ then
D2<=”1111001″;
elsif A2=”0010″ then
D2<=”0100100″;
elsif A2=”0011″ then
D2<=”0110000″;
elsif A2=”0100″ then
D2<=”0011001″;
elsif A2=”0101″ then
D2<=”0010010″;
elsif A2=”0110″ then
D2<=”0000010″;
elsif A2=”0111″ then
D2<=”1111000″;
elsif A2=”1000″ then
D2<=”0000000″;
elsif A2=”1001″ then
D2<=”0011000″;
elsif A2=”1010″ then
D2<=”0001000″;

elsif A2=”1011″ then
D2<=”0000011″;
elsif A2=”1100″ then
D2<=”1000110″;
elsif A2=”1101″ then
D2<=”0100001″;
elsif A2=”1110″ then
D2<=”0000110″;
else
D2<=”0001110″;
end if;
end process;
process(clk,reset)
begin
if reset=’1′ then
DPY1<=”1110110″;
DPY2<=”1110110″;
elsif clk’event and clk=’1′ then
if WDP=’1′ then
DPY1<=D1;
DPY2<=D2; end if; end if; end process; end; –*********************************** –* Description :Fsel gate Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity fsel is port(FLR, b: in std_logic_vector (2 downto 0); X_sig: in std_logic_vector(4 downto 0); b3: in std_logic; JC: out std_logic); end; Architecture Fsel_Block of fsel is signal JC_sig : std_logic ; begin process(FLR, X_sig, b) begin case b is when “000” => JC_sig <= FLR (1); when “001” => JC_sig <= FLR (2); when “010” => JC_sig <= FLR (0); when “011” => JC_sig <= X_sig (0); when “100” => JC_sig <= X_sig(1); when “101” => JC_sig <= X_sig(2); when “110” => JC_sig <= X_sig(3); when others => JC_sig <= X_sig(4);
end case;
end process;
JC <= b3 xor JC_sig;
end;

–*****************************************
–* DESCRIPTION : Interrupt Mask

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.ALL;

entity IMASK is
port( clk, reset, WMR : in std_logic;
IR_B0, IRQ_sig, EIN, DIN : in std_logic;
INT : out std_logic);
end;

Architecture EX1 of IMASK is
signal Q1, Q2, Q3 : std_logic;
begin
process(clk,reset)
begin
if reset = ‘1’ then
Q1<=’0′;
Q3<=’1′;
elsif clk’event and clk =’1′ then
if WMR=’1′ then
Q1<=IR_B0;
end if;
if Q2 =’1′ then
Q3<=EIN;
end if;
end if;
end process;

INT<=IRQ_sig and Q1 and Q3;
Q2<=EIN or DIN;
end;

–***********************************************
–* DESCRIPTION : Control Unit

Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;

Entity CU is
port(clk, reset, int, jc : in std_logic;
R,W, REX, RRG : out std_logic;
copy_flag, re_flag : out std_logic;
WRG, WBR, RAC, WAC : out std_logic;
WFL, WIR, WPC, IPC : out std_logic;
WDP, WHA, WLA, SAR : out std_logic;
ISP, DSP, WST, WMR : out std_logic;
DIN, EIN, selekt : out std_logic;
OPC : in std_logic_vector(4 downto 0);
AOP : out std_logic_vector(4 downto 0);
SPA : out std_logic_vector(1 downto 0));
end;
Architecture ex1 of CU is
type state_type is (s0,s1,s1b,s2,s3,s4,s5,s6,s7,s8,s9);
signal state: state_type;
begin
process(clk,reset)
begin
if reset =’1′ then
state<=s0;
R<=’0′;
W<=’0′;
AOP<=(others=>’0′);
SPA<=”00″;
REX<=’0′;
RRG<=’0′;
WRG<=’0′;
WBR<=’0′;
RAC<=’0′;
WAC<=’0′;
WFL<=’0′;
WIR<=’0′;
WPC<=’0′;
IPC<=’0′;
WDP<=’0′;
WHA<=’0′;
WLA<=’0′;
SAR<=’0′;
ISP<=’0′;
DSP<=’0′;
WST<=’0′;
WMR<=’0′;
DIN<=’0′;
EIN<=’1′;
copy_flag<=’0′;
re_flag<=’0′;
selekt<=’0′;
elsif clk’event and clk =’1′ then
R<=’0′;
W<=’0′;
AOP<=(others=>’0′);
SPA<=”00″;
REX<=’0′;
RRG<=’0′;
WRG<=’0′;
WBR<=’0′;
RAC<=’0′;
WAC<=’0′;
WFL<=’0′;
WIR<=’0′;
WPC<=’0′;
IPC<=’0′;
WDP<=’0′;
WHA<=’0′;
WLA<=’0′;
SAR<=’0′;
ISP<=’0′;
DSP<=’0′;
WST<=’0′;
WMR<=’0′;
DIN<=’0′;
EIN<=’0′;
copy_flag<=’0′;
re_flag<=’0′;
selekt<=’0′; case state is when s0=> if int=’1′ then — Test for interrupt
state<=s8;
DIN<=’1′;
else
state<=s1; — Change to the next state end if; when s1=> state<=s1b; — Change to the next state
R<=’1′;
WIR<=’1′;
IPC<=’1′; when s1b=> state<=s2; when s2=> if OPC= 0 then — (NOP)
state<=s0; — Change state to S0
elsif OPC=1 then — (STAD)
state<=s0; — Change state to S0
WDP<=’1′;
elsif OPC=4 then — (LDA r)
state<=s0; — Change state to S0
RRG<=’1′;
WAC<=’1′;
WFL<=’1′;
AOP<=”00001″; — Y = A
elsif OPC=5 then — (STA r)
state<=s0; — Change state to S0
RAC<=’1′;
WRG<=’1′;
AOP<=”00001″; — Y = A
elsif OPC=6 then — (DIN, EIN)
state<=s0; — Change state to S0
WMR<=’1′;
elsif OPC=7 then — (SRB b)
state<=s0; — Change state to S0
WBR<=’1′;
elsif OPC=12 then — (LDAX rp)
state<=s3;
RRG<=’1′;
WHA<=’1′;
elsif OPC=13 then — (STAX rp)
state<=s3; — Change state to S3
RRG<=’1′;
WHA<=’1′;
elsif OPC=14 then — (RTS)
state<=s3; — Change state to S3
DSP<=’1′;
elsif OPC=15 then — (RTI)
state<=s3; — Change state to S3
DSP<=’1′;
elsif OPC=17 then — (JSR)
state<=s3; — Change state to S3
copy_flag <=’1′;

–****************************************
— ***** (Villkorliga hopp) *****
–****************************************

elsif OPC(4 downto 1)=”1001″ then
if jc=’1′ then
state<=s3;
else
state<=s9;
IPC<=’1′;
end if;
elsif OPC=22 then — (INCA)
state<=s0; — Change state to S0
RAC<=’1′;
WAC<=’1′;
WFL<=’1′;
AOP<=(1=>’1′,others=>’0′); — acc = acc + 1
elsif OPC=23 then — (INCR r)
state<=s0; — Change state to S0
RRG<=’1′;
WRG<=’1′;
WFL<=’1′;
AOP<=(1=>’1′,others=>’0′); — Reg = Reg + 1
elsif OPC=24 then — (DECA)
state<=s0; — Change state to S0
RAC<=’1′;
WAC<=’1′;
WFL<=’1′;
AOP<=”00011″; — Acc = acc – 1
elsif OPC=25 then — (DECR r)
state<=s0; — Change state to S0
RRG<=’1′;
WRG<=’1′;
WFL<=’1′;
AOP<=”00011″; — Reg = Reg – 1
elsif OPC=26 then — (ADD r)
state<=s0; — Change state to S0
RRG<=’1′;
WAC<=’1′;
WFL<=’1′;
AOP<=”00110″; — ack + reg
elsif OPC=28 then — (SUB r) till s0
state<=s0; — Change state to S0
RRG<=’1′;
WAC<=’1′;
WFL<=’1′;
AOP<=”00111″; — Y = A – B
elsif OPC=29 then — (NOTA)
state<=s0; — Change state to S0
RAC<=’1′;
WAC<=’1′;
WFL<=’1′;
AOP<=”01000″; — Y = not A
elsif OPC=31 then — (CMP r)
state<=s0; — Change state to S0
RRG<=’1′;
WFL<=’1′;
AOP<=”00111″; — Y = A – B
else — For the others change
state<=s3; — to the next state end if; when s3=> if OPC=2 then — (LDA konstant)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”00001″; — Y = A
WAC<=’1′;
IPC<=’1′;
elsif OPC=3 then — (LDR r, konstant)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”00001″; — Y = A
WRG<=’1′;
IPC<=’1′;
elsif OPC = 8 then — (LDA adr)
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC = 9 then — (STA adr)
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC = 10 then — (LDA r,konst)
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC = 11 then — (STR r,adr)
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC=12 then — (LDAX rp)
state<=s4; — Change to the next state
selekt <=’1′;
RRG<=’1′;
WLA<=’1′;
elsif OPC=13 then — (STAX rp)
state<=s4; — Change to the next state
selekt <=’1′;
RRG<=’1′;
WLA<=’1′;
elsif OPC=14 then — RTS
state<=s4; — Change to S4
SPA<=”01″;
WPC<=’1′;
elsif OPC=15 then — (RTI)
state<=s0; — Change state to S0
re_flag <=’1′; — recopy to flag
SPA<=”01″; — Select stack address
WPC<=’1′;
EIN<=’1′;
elsif OPC = 16 then — (JMP adr)
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC=17 then — (JSR adr)
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC = 18 then
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC = 19 then
state<=s4; — Change to the next state
R<=’1′;
REX<=’1′;
WHA<=’1′;
IPC<=’1′;
elsif OPC=20 then — (ANDA konstant)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”10000″; — Y = A and B 10000
WFL<=’1′;
WAC<=’1′;
IPC<=’1′;
elsif OPC=21 then — (ORA konstant)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”11000″; — Y = A or B 11000
WFL<=’1′;
WAC<=’1′;
IPC<=’1′;
elsif OPC=27 then — (ADD konstant)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”00110″; — Y = A + B
WAC<=’1′;
WFL<=’1′;
IPC<=’1′;
elsif OPC=30 then — (CMP konstant)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”00111″; — Y = A – B
WFL<=’1′;
IPC<=’1′; end if; when s4=> if OPC=12 then — (LDAX rp)
state<=s5; — Change to the next state
SAR<=’1′;
elsif OPC =13 then
state<=s5; — Change to the next state
SAR<=’1′;
elsif OPC=14 then
state <= s0;
IPC <= ‘1’;
elsif OPC=17 then
state<=s5;
WST<=’1′;
ISP <= ‘1’;
else
state<=s5; end if; when s5=> if OPC=12 then — (LDAX rp)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”00001″; — Y = A
WAC<=’1′;
WFL<=’1′;
SAR<=’1′;
elsif OPC=13 then — (STAX rp)
state<=s0; — Change state to S0
W<=’1′;
RAC<=’1′;
SAR<=’1′;
elsif OPC = 16 then
state<=s0;
R<=’1′;
REX<=’1′;
SPA<=”00″; –Stacken ska lagra återhopsadressen
WPC<=’1′;
elsif OPC = 17 then
state<=s0;
R <=’1′;
REX <=’1′;
SPA <=”00″; –Stacken ska lagra återhopsadressen
WPC <=’1′;
elsif OPC = 18 then
state<= s0;
R <=’1′;
REX<=’1′;
SPA<=”00″; –Stacken ska lagra återhopsadressen
WPC<=’1′;
elsif OPC = 19 then
state<=s0;
R <=’1′;
REX<=’1′;
SPA<=”00″; –Stacken ska lagra återhopsadressen
WPC<=’1′;
else
state<= s6;
R<=’1′;
REX<=’1′;
WLA<=’1′;
IPC<=’1′; end if; when s6=> state<=s7; — Change to the next state
SAR<=’1′; when s7=> if OPC=8 then — (LDA adr)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”00001″; — Y = A
WFL<=’1′;
WAC<=’1′;
SAR<=’1′;

elsif OPC=9 then — (STA adr) till s0
state<=s0; — Change state to S0
W<=’1′;
RAC<=’1′;
SAR<=’1′;
elsif OPC=10 then — (LDR r, adr)
state<=s0; — Change state to S0
R<=’1′;
REX<=’1′;
AOP<=”00001″; — Y = A
WFL<=’1′;
WRG<=’1′;
SAR<=’1′;
elsif OPC=11 then — (STR r,adr)
state<=s0; — Change state to S0
W<=’1′;
RRG<=’1′;
SAR<=’1′; end if; –***************************************** –*** INTERRUPT *** –***************************************** when s8=> state<=s0; — Change state to S0
WST<=’1′;
SPA<=”11″; — Select address “0008”
WPC<=’1′;
ISP<=’1′;
copy_flag<=’1′; –***************************************** –*** Om JC = 0 *** –***************************************** when s9=> state<=s0; — Change state to S0
IPC<=’1′; end case; end if; end process; end; –* DESCRIPTION : Central Processing Unit Library ieee; Use ieee.std_logic_1164.ALL; Use ieee.std_logic_unsigned.all; entity CPU_CORE is port ( clk, reset, IRQ : in std_logic; X : in std_logic_vector(4 downto 0); Indata : in std_logic_vector(7 downto 0); Utdata : out std_logic_vector(7 downto 0); R,W : out std_logic; Adress : out std_logic_vector(15 downto 0); DPY1, DPY2 : out std_logic_vector(6 downto 0)); end; architecture EX1 of CPU_CORE is signal INT, JC, REX, RRG : std_logic; signal WRG, WBR, RAC, WAC : std_logic; signal WFL, WIR, WPC, IPC : std_logic; signal WDP, WHA, WLA, SAR : std_logic; signal ISP, DSP, WST, WMR : std_logic; signal selekt : std_logic; signal DIN, EIN, CF, RF : std_logic; signal ack_sig : std_logic_vector(7 downto 0); signal IRQS : std_logic; signal Data_bus : std_logic_vector(7 downto 0); signal Reg_to_mux : std_logic_vector(7 downto 0); signal instr5 : std_logic_vector(4 downto 0); signal instr : std_logic_vector(2 downto 0); signal From_Y : std_logic_vector(7 downto 0); signal SI : std_logic_vector(15 downto 0); signal SO : std_logic_vector(15 downto 0); signal XS : std_logic_vector(4 downto 0); signal AOP : std_logic_vector(4 downto 0); signal SPA : std_logic_vector(1 downto 0); signal FL : std_logic_vector(2 downto 0); signal ST : std_logic_vector(3 downto 0); component Muxar — (1) port ( REX,RAC,RRG : in std_logic; ACC,Dout,Data_in :in std_logic_vector(7 downto 0); Data_buss : out std_logic_vector(7 downto 0)); end component; –=============================================================== component ALU — (2) port( databuss: in std_logic_vector (7 downto 0); AOP: in std_logic_vector (4 downto 0); WFL: in std_logic; WAC: in std_logic; clk: in std_logic; reset: in std_logic; copy_flag: in std_logic; re_flag: in std_logic; ack: out std_logic_vector (7 downto 0); Y: out std_logic_vector (7 downto 0); Flag: inout std_logic_vector (2 downto 0)); end component; –=============================================================== component REG — (3) port(clk, reset, selekt: in std_logic; WRG: in std_logic; WBR: in std_logic; addr: in std_logic_vector (2 downto 0); D_IN: in std_logic_vector (7 downto 0); D_OUT: out std_logic_vector (7 downto 0)); end component; –=============================================================== component IR — (4) port(clk, reset, WIR: in std_logic; Data: in std_logic_vector (7 downto 0); IR5: out std_logic_vector (4 downto 0); IR3: out std_logic_vector (2 downto 0)); End component; –=============================================================== component iq — (5) port (clk, reset, IRQ : in std_logic; X_in : in std_logic_vector (4 downto 0); IRQ_till_IMASK : out std_logic; X_till_FSEL : out std_logic_vector (4 downto 0)); end component; component Addr –(6) port(databus : in std_logic_vector (7 downto 0); stack_in : in std_logic_vector (15 downto 0); SPA : in std_logic_vector (1 downto 0); WHA : in std_logic; WLA : in std_logic; WPC : in std_logic; IPC : in std_logic; SAR : in std_logic; reset : in std_logic; clk : in std_logic; stack_out : out std_logic_vector (15 downto 0); address_out : out std_logic_vector (15 downto 0)); end component; –=============================================================== component DISPLAY –(7) port( clk, reset, WDP : in std_logic; ACC : in std_logic_vector(7 downto 0); DPY1,DPY2 : out std_logic_vector(6 downto 0)); end component; –=============================================================== component fsel — (8) port(FLR, b: in std_logic_vector (2 downto 0); X_sig: in std_logic_vector(4 downto 0); b3: in std_logic; JC: out std_logic); end component; –=============================================================== component IMASK –(9) port(clk, reset, WMR : in std_logic; IR_B0, IRQ_sig, EIN, DIN : in std_logic; INT : out std_logic); end component; –=============================================================== component CU –(10) port(clk, reset, int, jc : in std_logic; R,W, REX, RRG : out std_logic; copy_flag, re_flag : out std_logic; WRG, WBR, RAC, WAC : out std_logic; WFL, WIR, WPC, IPC : out std_logic; WDP, WHA, WLA, SAR : out std_logic; ISP, DSP, WST, WMR : out std_logic; DIN, EIN, selekt : out std_logic; OPC : in std_logic_vector(4 downto 0); AOP : out std_logic_vector(4 downto 0); SPA : out std_logic_vector(1 downto 0)); end component; –=============================================================== component stack –(11) port(clk, wst : in std_logic; sp : in std_logic_vector(3 downto 0); din : in std_logic_vector(15 downto 0); dout : out std_logic_vector(15 downto 0)); end component; –=============================================================== component SP –(12) port(clk,reset,isp,dsp : in std_logic; sp : out std_logic_vector(3 downto 0)); end component; –=============================================================== — ******* Komenteras bort vid syntesen *********** FOR U1 : Muxar Use Entity work.Muxar(Muxar_Block); FOR U2 : ALU Use Entity work.ALU(RTL); FOR U3 : REG Use Entity work.REG(REGBANK); FOR U4 : IR Use Entity work.IR(Instruction); FOR U5 : iq Use Entity work.iq(rtl); FOR U6 : Addr Use Entity work.Addr(block_7); FOR U7 : DISPLAY Use Entity work.DISPLAY(rtl); FOR U8 : fsel Use Entity work.fsel(Fsel_Block); FOR U9 : IMASK Use Entity work.IMASK(EX1); FOR U10 : CU Use Entity work.CU(ex1); FOR U11 : stack Use Entity work.stack(rtl); FOR U12 : SP Use Entity work.SP(rtl); begin U1 : Muxar PORT MAP (REX=>REX, RAC=>RAC, RRG=>RRG, Data_in=>indata, Dout=>Reg_to_mux,
ACC=>ack_sig, data_buss=>data_bus);
U2 : ALU
PORT MAP (databuss=>data_bus, AOP=>AOP, WFL=>WFL, WAC=>WAC,
clk=>clk, reset=>reset, copy_flag=>CF, re_flag=>RF, Y=>From_y,
flag=>FL, ack=>ack_sig);
U3 : REG
PORT MAP (clk=>clk, reset=>reset, WRG=>WRG, WBR=>WBR, selekt=>selekt,
D_IN=>from_y, addr=>instr, d_out=>reg_to_mux);
U4 : IR
PORT MAP (clk=>clk, reset=>reset, WIR=>WIR, Data=>Indata,
IR5=>instr5, IR3=>instr);
U5 : iq
PORT MAP (clk=>clk, reset=>reset, X_in=>X, IRQ=>IRQ,
X_till_FSEL=>XS, IRQ_till_IMASK=>IRQS);
U6 : Addr
PORT MAP (databus=>data_bus, stack_in=>SI, WHA=>WHA,
WLA=>WLA, SPA=>SPA, WPC=>WPC, IPC=>IPC, SAR=>SAR,
reset=>reset, clk=>clk, stack_out=>SO,
address_out=>Adress);
U7 : DISPLAY
PORT MAP (clk=>clk, reset=>reset, WDP=>WDP, ACC=>ack_sig,
DPY1=>DPY1, DPY2=>DPY2);
U8 : Fsel
PORT MAP (FLR=>FL, b=>instr, b3=>instr5(0), X_sig=>XS, JC=>JC);
U9 : IMASK
PORT MAP (clk=>clk, reset=>reset, WMR=>WMR, IR_B0=>instr(0),
IRQ_sig=>IRQS, EIN=>EIN, DIN=>DIN, INT=>INT);
U10 : CU
PORT MAP (clk=>clk, reset=>reset, INT=>INT, JC=>JC, R=>R, W=>W, WAC=>WAC,REX=>REX,
RRG=>RRG, WFL=>WFL, WIR=>WIR, WPC=>WPC, WBR=>WBR, IPC=>IPC, WDP=>WDP,
WHA=>WHA, WLA=>WLA, SAR=> SAR, RAC=>RAC, ISP=>ISP, DSP=>DSP, WST=>WST,
WMR=>WMR, DIN=>DIN, EIN=>EIN, OPC=>instr5, AOP=>AOP, SPA=>SPA, WRG=>WRG,
copy_flag=>CF, re_flag=>RF, selekt=>selekt);
U11 : stack
PORT MAP (clk => clk, WST=>WST, SP=>ST, Din=>SO, dout=>SI);

U12 : SP
PORT MAP (DSP=>DSP, clk=>clk, reset=>reset, ISP=>ISP, SP=>ST);
utdata <= Data_bus;
end;

–* DESCRIPTION : Main Central Processing Unit

Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.all;

entity CPU_TOP is
port ( clk, reset, IRQ : in std_logic;
R , W : out std_logic;
X : in std_logic_vector(4 downto 0);
D : inout std_logic_vector(7 downto 0);
A : out std_logic_vector(15 downto 0);
DPY1, DPY2 : out std_logic_vector(6 downto 0));
end;
architecture RTL of CPU_TOP is
component CPU_CORE
port ( clk, reset, IRQ : in std_logic;
X : in std_logic_vector(4 downto 0);
Indata : in std_logic_vector(7 downto 0);
Utdata : out std_logic_vector(7 downto 0);
R , W : out std_logic;
Adress : out std_logic_vector(15 downto 0);
DPY1, DPY2 : out std_logic_vector(6 downto 0));
end component;
signal w_b : std_logic;
signal Utdata : std_logic_vector(7 downto 0);
signal indata : std_logic_vector(7 downto 0);
FOR U1 : CPU_CORE Use Entity work.CPU_CORE(EX1);

begin

D <= Utdata when W_b = ‘1’ else (others=>’Z’);
indata <= D; U1 : CPU_CORE port map ( clk=>clk, reset=>reset, IRQ=>IRQ, X=>X,
R=>R, DPY1=>DPY1, DPY2=>DPY2, W=>W_b, Utdata=>Utdata,
Adress=>A, Indata=>indata);

W<=w_b; end; –* DESCRIPTION : Test Main Central Processing Unit Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; entity test_cpu_top is end; Architecture behv of test_cpu_top is component ram port( a: in std_logic_vector(12 downto 0); rw_n,dsbl,ce_n: in std_logic; d:inout std_logic_vector(7 downto 0)); end component; component rom port( a: in std_logic_vector(14 downto 0); dsbl,ce_n: in std_logic; d:out std_logic_vector(7 downto 0)); end component; component CPU_TOP port ( clk, reset, IRQ : in std_logic; R , W : out std_logic; X : in std_logic_vector(4 downto 0); D : inout std_logic_vector(7 downto 0); A : out std_logic_vector(15 downto 0); DPY1, DPY2 : out std_logic_vector(6 downto 0)); end component; signal clk : std_logic := ‘1’; signal reset : std_logic := ‘1’; signal IRQ : std_logic; signal X : std_logic_vector(4 downto 0); signal Rw_n, ce_n_rom, ce_n_ram : std_logic; signal R, w : std_logic; signal adress : std_logic_vector(15 downto 0); signal dsbl_ram, dsbl_rom : std_logic; signal D : std_logic_vector(7 downto 0):=(others=>’H’);
signal DPY1 : std_logic_vector(6 downto 0);
signal DPY2 : std_logic_vector(6 downto 0);

for U1 : ram USE entity work.ram(behv);
for U2 : rom USE entity work.rom(behv);
for U3 : CPU_TOP USE entity work.CPU_TOP(RTL);

begin
clk <= not clk after 50 ns;
reset <= ‘0’ after 75 ns;
X <= (others => ‘0’);
IRQ <= ‘0’,
‘1’ after 350 us,
‘0’ after 450 us;

rw_n <= not w;
ce_n_rom<= adress(15);
dsbl_rom <= not (not adress(15) and R);
ce_n_ram <= not adress(15);
dsbl_ram <= not(adress(15) and R);
D <= (others=>’H’);

U1 : ram
port map(a=>adress(12 downto 0), rw_n=>rw_n, dsbl=>dsbl_ram,
ce_n=>ce_n_ram, d=>D );

U2 : rom
port map(a=>adress(14 downto 0), dsbl=>dsbl_rom, ce_n=>ce_n_rom, d=>D);

U3 : CPU_TOP
port map(clk=>clk, reset=>reset, IRQ=>IRQ, X=>X,
D=>D, R=>R, W=>W, A=>adress, DPY1=>DPY1, DPY2=>DPY2);

end;

PLACE AND ROUTE
PAR: Xilinx Place And Route M1.5.25.
Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.

Tue Mar 2 14:18:52 1999

par -w -ol 4 -d 0 map.ncd CPU_TOP.ncd CPU_TOP.pcf

Constraints file: CPU_TOP.pcf

Loading device database for application par from file “map.ncd”.
“CPU_TOP” is an NCD, version 2.27, device xc4006e, package pc84, speed -2
Loading device for application par from file ‘4006e.nph’ in environment
/usr/local/viewlogic/alliance1.51i.
Device speed data version: x1_0.96 PRELIMINARY.

Resolved that IOB <A> must be placed at site P77.
Place IOB A in site P77.
Resolved that IOB <A> must be placed at site P5.
Place IOB A in site P5.
Resolved that IOB <A> must be placed at site P6.
Place IOB A in site P6.
Resolved that IOB <A> must be placed at site P7.
Place IOB A in site P7.
Resolved that IOB <A> must be placed at site P8.
Place IOB A in site P8.
Resolved that IOB <A> must be placed at site P9.
Place IOB A in site P9.
Resolved that IOB <A> must be placed at site P10.
Place IOB A in site P10.
Resolved that IOB <A> must be placed at site P78.
Place IOB A in site P78.
Resolved that IOB <A> must be placed at site P79.
Place IOB A in site P79.
Resolved that IOB <A> must be placed at site P80.
Place IOB A in site P80.
Resolved that IOB <A> must be placed at site P81.
Place IOB A in site P81.
Resolved that IOB <A> must be placed at site P82.
Place IOB A in site P82.
Resolved that IOB <A> must be placed at site P83.
Place IOB A in site P83.
Resolved that IOB <A> must be placed at site P84.
Place IOB A in site P84.
Resolved that IOB <A> must be placed at site P3.
Place IOB A in site P3.
Resolved that IOB <A> must be placed at site P4.
Place IOB A in site P4.
Resolved that CLKIOB must be placed at site P13.
Place CLKIOB clk in site P13.
Resolved that IOB <D> must be placed at site P71.
Place IOB D in site P71.
Resolved that IOB <D> must be placed at site P69.
Place IOB D in site P69.
Resolved that IOB <D> must be placed at site P67.
Place IOB D in site P67.
Resolved that IOB <D> must be placed at site P65.
Place IOB D in site P65.
Resolved that IOB <D> must be placed at site P61.
Place IOB D in site P61.
Resolved that IOB <D> must be placed at site P59.
Place IOB D in site P59.
Resolved that IOB <D> must be placed at site P58.
Place IOB D in site P58.
Resolved that IOB <D> must be placed at site P56.
Place IOB D in site P56.
Resolved that IOB <DPY1> must be placed at site P23.
Place IOB DPY1 in site P23.
Resolved that IOB <DPY1> must be placed at site P24.
Place IOB DPY1 in site P24.
Resolved that IOB <DPY1> must be placed at site P25.
Place IOB DPY1 in site P25.
Resolved that IOB <DPY1> must be placed at site P26.
Place IOB DPY1 in site P26.
Resolved that IOB <DPY1> must be placed at site P27.
Place IOB DPY1 in site P27.
Resolved that IOB <DPY1> must be placed at site P28.
Place IOB DPY1 in site P28.
Resolved that IOB <DPY1> must be placed at site P29.
Place IOB DPY1 in site P29.
Resolved that IOB <DPY2> must be placed at site P44.
Place IOB DPY2 in site P44.
Resolved that IOB <DPY2> must be placed at site P45.
Place IOB DPY2 in site P45.
Resolved that IOB <DPY2> must be placed at site P46.
Place IOB DPY2 in site P46.
Resolved that IOB <DPY2> must be placed at site P47.
Place IOB DPY2 in site P47.
Resolved that IOB <DPY2> must be placed at site P48.
Place IOB DPY2 in site P48.
Resolved that IOB <DPY2> must be placed at site P49.
Place IOB DPY2 in site P49.
Resolved that IOB <DPY2> must be placed at site P50.
Place IOB DPY2 in site P50.
Resolved that IOB must be placed at site P40.
Place IOB IRQ in site P40.
Resolved that IOB must be placed at site P68.
Place IOB R in site P68.
Resolved that IOB must be placed at site P35.
Place IOB reset in site P35.
Resolved that IOB must be placed at site P62.
Place IOB W in site P62.
Resolved that IOB <X> must be placed at site P18.
Place IOB X in site P18.
Resolved that IOB <X> must be placed at site P19.
Place IOB X in site P19.
Resolved that IOB <X> must be placed at site P20.
Place IOB X in site P20.
Resolved that IOB <X> must be placed at site P38.
Place IOB X in site P38.
Resolved that IOB <X> must be placed at site P39.
Place IOB X in site P39.
Resolved that PRI-CLK must be placed at site BUFGP_TL.
Place PRI-CLK C1002 in site BUFGP_TL.

Device utilization summary:
Number of External IOBs 47 out of 61 77%
Flops: 0
Latches: 0
Number of Global Buffer IOBs 1 out of 8 12%
Flops: 0
Latches: 0
Number of CLBs 243 out of 256 94%
Total CLB Flops: 251 out of 512 49%
4 input LUTs: 391 out of 512 76%
3 input LUTs: 112 out of 256 43%
Number of PRI-CLKs 1 out of 4 25%

Overall effort level (-ol): 4 (set by user)
Placer effort level (-pl): 4 (default)
Placer cost table entry (-t): 1
Router effort level (-rl): 4 (default)
Timing method (-kpaths|-dfs): -kpaths (default)
Starting initial Timing Analysis. REAL time: 6 secs
Finished initial Timing Analysis. REAL time: 27 secs
Starting initial Placement phase. REAL time: 29 secs
Finished initial Placement phase. REAL time: 29 secs
Starting Constructive Placer. REAL time: 30 secs
Placer score = 609911
Placer score = 400018
Placer score = 319711
Placer score = 280506
Placer score = 237256
Placer score = 236567
Placer score = 209327
Placer score = 204279
Placer score = 197314
Placer score = 188072
Placer score = 186430
Placer score = 175456
Placer score = 170041
Placer score = 167513
Placer score = 165185
Placer score = 162959
Placer score = 160516
Placer score = 159928
Placer score = 158832
Finished Constructive Placer. REAL time: 8 mins 11 secs

Writing design to file “CPU_TOP.ncd”.
Starting Optimizing Placer. REAL time: 8 mins 12 secs
Optimizing ..
Swapped 3 comps.
Xilinx Placer [1] 158288 REAL time: 8 mins 33 secs
Finished Optimizing Placer. REAL time: 8 mins 33 secs
Writing design to file “CPU_TOP.ncd”.
Total REAL time to Placer completion: 8 mins 35 secs
Total CPU time to Placer completion: 8 mins 31 secs
0 connection(s) routed; 2001 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 9 mins 52 secs
Starting iterative routing.
Routing active signals.
End of iteration 1
2001 successful; 0 unrouted; (1525315) REAL time: 11 mins 47 secs
Improving timing.
End of iteration 2
2001 successful; 0 unrouted; (19776) REAL time: 13 mins 44 secs
Routing PWR/GND nets.
Power and ground nets completely routed.
End of iteration 3
2001 successful; 0 unrouted; (0) REAL time: 15 mins 30 secs
Constraints are met.
Writing design to file “CPU_TOP.ncd”.
Starting cleanup
Improving routing.
End of cleanup iteration 1
2001 successful; 0 unrouted; (0) REAL time: 17 mins 21 secs
Writing design to file “CPU_TOP.ncd”.
Total REAL time: 17 mins 24 secs
Total CPU time: 17 mins 6 secs
End of route. 2001 routed (100.00%); 0 unrouted.
No errors found.
Completely routed.
Total REAL time to Router completion: 17 mins 28 secs
Total CPU time to Router completion: 17 mins 9 secs
Generating PAR statistics.
The Delay Summary Report
The Score for this design is: 807
The Number of signals not completely routed for this design is: 0
The Average Connection Delay for this design is: 4.158 ns
The Average Connection Delay on critical nets is: 0.000 ns
The Average Clock Skew for this design is: 0.062 ns
The Maximum Pin Delay is: 23.276 ns
The Average Connection Delay on the 10 Worst Nets is: 19.598 ns
Listing Pin Delays by value: (ns)

d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50
——— ——— ——— ——— ——— ———
1851 139 11 0 0 0

Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
——————————————————————————–
Constraint | Requested | Actual | Logic
| | | Levels
——————————————————————————–
TS0 = MAXDELAY FROM TIMEGRP “pads” TO TIM | 66.000ns | 27.033ns | 3
EGRP “pads” 66 nS | | |
——————————————————————————–
TS1 = MAXDELAY FROM TIMEGRP “pads” TO TIM | 66.000ns | 43.730ns | 2
EGRP “tgrp_0_DFF” 66 nS | | |
——————————————————————————–
TS2 = MAXDELAY FROM TIMEGRP “tgrp_0_DFF” | 66.000ns | 47.386ns | 7
TO TIMEGRP “pads” 66 nS | | |
——————————————————————————–
TS3 = MAXDELAY FROM TIMEGRP “tgrp_0_DFF” | 66.000ns | 62.926ns | 12
TO TIMEGRP “tgrp_0_DFF” 66 nS | | |
——————————————————————————–
All constraints were met.
Writing design to file “CPU_TOP.ncd”.
All signals are completely routed.
Total REAL time to PAR completion: 17 mins 40 secs
Total CPU time to PAR completion: 17 mins 20 secs
PAR done.
PAR: Xilinx Place And Route M1.5.25.
Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.
Tue Mar 2 14:36:31 1999

Xilinx PAD Specification File
Xilinx PAD Specification File
*****************************
Input file: map.ncd
Output file: CPU_TOP.ncd
Part type: xc4006e
Speed grade: -2
Package: pc84

Tue Mar 2 14:36:31 1999

Pinout by Pin Name:
+————————————————+———–+————–+
| Pin Name | Direction | Pin Number |
+————————————————+———–+————–+
| A | OUTPUT | P77 |
| A | OUTPUT | P5 |
| A | OUTPUT | P6 |
| A | OUTPUT | P7 |
| A | OUTPUT | P8 |
| A | OUTPUT | P9 |
| A | OUTPUT | P10 |
| A | OUTPUT | P78 |
| A | OUTPUT | P79 |
| A | OUTPUT | P80 |
| A | OUTPUT | P81 |
| A | OUTPUT | P82 |
| A | OUTPUT | P83 |
| A | OUTPUT | P84 |
| A | OUTPUT | P3 |
| A | OUTPUT | P4 |
| D | BIDIR | P71 |
| D | BIDIR | P69 |
| D | BIDIR | P67 |
| D | BIDIR | P65 |
| D | BIDIR | P61 |
| D | BIDIR | P59 |
| D | BIDIR | P58 |
| D | BIDIR | P56 |
| DPY1 | OUTPUT | P23 |
| DPY1 | OUTPUT | P24 |
| DPY1 | OUTPUT | P25 |
| DPY1 | OUTPUT | P26 |
| DPY1 | OUTPUT | P27 |
| DPY1 | OUTPUT | P28 |
| DPY1 | OUTPUT | P29 |
| DPY2 | OUTPUT | P44 |
| DPY2 | OUTPUT | P45 |
| DPY2 | OUTPUT | P46 |
| DPY2 | OUTPUT | P47 |
| DPY2 | OUTPUT | P48 |
| DPY2 | OUTPUT | P49 |
| DPY2 | OUTPUT | P50 |
| IRQ | INPUT | P40 |
| R | OUTPUT | P68 |
| W | OUTPUT | P62 |
| X | INPUT | P18 |
| X | INPUT | P19 |
| X | INPUT | P20 |
| X | INPUT | P38 |
| X | INPUT | P39 |
| clk | INPUT | P13 |
| reset | INPUT | P35 |
+————————————————+———–+————–+

| Dedicated or Special Pin Name | Pin Number |
+————————————————————+————–+
| /PROG | P55 |
| CCLK | P73 |
| DONE | P53 |
| GND | P52 |
| GND | P12 |
| GND | P43 |
| GND | P64 |
| GND | P76 |
| GND | P31 |
| GND | P21 |
| GND | P1 |
| M0 | P32 |
| M1 | P30 |
| M2 | P34 |
| TDO | TDO |
| TDO | P75 |
| VCC | P33 |
| VCC | P2 |
| VCC | P22 |
| VCC | P11 |
| VCC | P54 |
| VCC | P42 |
| VCC | P63 |
| VCC | P74 |
+————————————————————+————–+

Pinout by Pin Number:
+————–+———————————–+———–+————+
| Pin Number | Pin Name | Direction | Constraint |
+————–+———————————–+———–+————+
| P1 | GND | | |
| P2 | VCC | | |
| P3 | A | OUTPUT | LOCATED |
| P4 | A | OUTPUT | LOCATED |
| P5 | A | OUTPUT | LOCATED |
| P6 | A | OUTPUT | LOCATED |
| P7 | A | OUTPUT | LOCATED |
| P8 | A | OUTPUT | LOCATED |
| P9 | A | OUTPUT | LOCATED |
| P10 | A | OUTPUT | LOCATED |
| P11 | VCC | | |
| P12 | GND | | |
| P13 | clk | INPUT | LOCATED |
| P14 | | | |
| P15 | | | |
| P16 | | | |
| P17 | | | |
| P18 | X | INPUT | LOCATED |
| P19 | X | INPUT | LOCATED |
| P20 | X | INPUT | LOCATED |
| P21 | GND | | |
| P22 | VCC | | |
| P23 | DPY1 | OUTPUT | LOCATED |
| P24 | DPY1 | OUTPUT | LOCATED |
| P25 | DPY1 | OUTPUT | LOCATED |
| P26 | DPY1 | OUTPUT | LOCATED |
| P27 | DPY1 | OUTPUT | LOCATED |
| P28 | DPY1 | OUTPUT | LOCATED |
| P29 | DPY1 | OUTPUT | LOCATED |
| P30 | M1 | | |
| P31 | GND | | |
| P32 | M0 | | |
| P33 | VCC | | |
| P34 | M2 | | |
| P35 | reset | INPUT | LOCATED |
| P36 | | | |
| P37 | | | |
| P38 | X | INPUT | LOCATED |
| P39 | X | INPUT | LOCATED |
| P40 | IRQ | INPUT | LOCATED |
| P41 | | | |
| P42 | VCC | | |
| P43 | GND | | |
| P44 | DPY2 | OUTPUT | LOCATED |
| P45 | DPY2 | OUTPUT | LOCATED |
| P46 | DPY2 | OUTPUT | LOCATED |
| P47 | DPY2 | OUTPUT | LOCATED |
| P48 | DPY2 | OUTPUT | LOCATED |
| P49 | DPY2 | OUTPUT | LOCATED |
| P50 | DPY2 | OUTPUT | LOCATED |
| P51 | | | |
| P52 | GND | | |
| P53 | DONE | | |
| P54 | VCC | | |
| P55 | /PROG | | |
| P56 | D | BIDIR | LOCATED |
| P57 | | | |
| P58 | D | BIDIR | LOCATED |
| P59 | D | BIDIR | LOCATED |
| P60 | | | |
| P61 | D | BIDIR | LOCATED |
| P62 | W | OUTPUT | LOCATED |
| P63 | VCC | | |
| P64 | GND | | |
| P65 | D | BIDIR | LOCATED |
| P66 | | | |
| P67 | D | BIDIR | LOCATED |
| P68 | R | OUTPUT | LOCATED |
| P69 | D | BIDIR | LOCATED |
| P70 | | | |
| P71 | D | BIDIR | LOCATED |
| P72 | | | |
| P73 | CCLK | | |
| P74 | VCC | | |
| P75 | TDO | | |
| P76 | GND | | |
| P77 | A | OUTPUT | LOCATED |
| P78 | A | OUTPUT | LOCATED |
| P79 | A | OUTPUT | LOCATED |
| P80 | A | OUTPUT | LOCATED |
| P81 | A | OUTPUT | LOCATED |
| P82 | A | OUTPUT | LOCATED |
| P83 | A | OUTPUT | LOCATED |
| P84 | A | OUTPUT | LOCATED |
| TDO | TDO | | |
+————–+———————————–+———–+————+

# Pinout constraints listing
# These constraints are in PCF grammar format
# and may be cut and pasted into the PCF file
# after the “SCHEMATIC END ;” statement to
# preserve this pinout for future design iterations.
#
COMP “A” LOCATE = SITE “P77” ;
COMP “A” LOCATE = SITE “P5” ;
COMP “A” LOCATE = SITE “P6” ;
COMP “A” LOCATE = SITE “P7” ;
COMP “A” LOCATE = SITE “P8” ;
COMP “A” LOCATE = SITE “P9” ;
COMP “A” LOCATE = SITE “P10” ;
COMP “A” LOCATE = SITE “P78” ;
COMP “A” LOCATE = SITE “P79” ;
COMP “A” LOCATE = SITE “P80” ;
COMP “A” LOCATE = SITE “P81” ;
COMP “A” LOCATE = SITE “P82” ;
COMP “A” LOCATE = SITE “P83” ;
COMP “A” LOCATE = SITE “P84” ;
COMP “A” LOCATE = SITE “P3” ;
COMP “A” LOCATE = SITE “P4” ;
COMP “D” LOCATE = SITE “P71” ;
COMP “D” LOCATE = SITE “P69” ;
COMP “D” LOCATE = SITE “P67” ;
COMP “D” LOCATE = SITE “P65” ;
COMP “D” LOCATE = SITE “P61” ;
COMP “D” LOCATE = SITE “P59” ;
COMP “D” LOCATE = SITE “P58” ;
COMP “D” LOCATE = SITE “P56” ;
COMP “DPY1” LOCATE = SITE “P23” ;
COMP “DPY1” LOCATE = SITE “P24” ;
COMP “DPY1” LOCATE = SITE “P25” ;
COMP “DPY1” LOCATE = SITE “P26” ;
COMP “DPY1” LOCATE = SITE “P27” ;
COMP “DPY1” LOCATE = SITE “P28” ;
COMP “DPY1” LOCATE = SITE “P29” ;
COMP “DPY2” LOCATE = SITE “P44” ;
COMP “DPY2” LOCATE = SITE “P45” ;
COMP “DPY2” LOCATE = SITE “P46” ;
COMP “DPY2” LOCATE = SITE “P47” ;
COMP “DPY2” LOCATE = SITE “P48” ;
COMP “DPY2” LOCATE = SITE “P49” ;
COMP “DPY2” LOCATE = SITE “P50” ;
COMP “IRQ” LOCATE = SITE “P40” ;
COMP “R” LOCATE = SITE “P68” ;
COMP “W” LOCATE = SITE “P62” ;
COMP “X” LOCATE = SITE “P18” ;
COMP “X” LOCATE = SITE “P19” ;
COMP “X” LOCATE = SITE “P20” ;
COMP “X” LOCATE = SITE “P38” ;
COMP “X” LOCATE = SITE “P39” ;
COMP “clk” LOCATE = SITE “P13” ;
COMP “reset” LOCATE = SITE “P35” ;